1. Field of the Invention
The present invention relates to memory controllers for use in personal computers, and more particularly, to memory controllers for cooperation with write-back cache units and bus masters.
2. Description of the Related Art
Personal computers are becoming more powerful with each passing day. From their origins as simple 8 bit microprocessors with limited memory spaces, personal computers have advanced to very powerful 32 bit microprocessors with very large memory spaces. In the early days of personal computers memory speeds were sufficient to maintain pace with the microprocessor and the memory architectures were relatively simple. As microprocessors have advanced and the memory spaces have enlarged, the microprocessor speed has outpaced the affordable increase in speed of the memory devices used in the main memory. Additionally, because of the increased size and speed requirements, the memory architecture has become quite complicated. Paged mode dynamic random access memories (DRAMs) and interleaving are common these days to help allow the use of relatively affordable DRAM devices with the very fast microprocessors currently available. This use of page mode devices and interleaving has of itself greatly complicated the memory controller which forms the interface between the microprocessor and the memory devices.
While the use of page mode DRAMs and interleaving has to some extent helped alleviate the speed difference between the microprocessor and the memories, they have not been sufficient. To this end the use of cache systems is becoming prevalent. In a cache system a very small amount of very high speed static RAM (SRAM) is used. The SRAM is designed such that it can operate at the full speed of the microprocessor, thus allowing full speed operation when the data is contained in the cache. It is a function of a cache controller to determine which data is contained in the relatively small amount of high speed memory from the total memory contained in the system and to selectively keep portions of the main memory in the cache memory according to some replacement technique, such as least recently used (LRU). The cache controller hopefully allows a high percentage, called the hit rate, of cycles to be run in zero wait states directly from the cache. However, in instances it may be necessary to actually access the main memory to obtain the data necessary for the cycle or provide data to the main memory. In general there are two types of cache architectures. The first is a write through architecture, where all write operations are not only stored in the cache but also passed directly through to the main memory. This architecture has the advantage of being relatively simple but also has the disadvantage that it increases the amount of bus bandwidth utilized by the microprocessor. In multiprocessor systems or in systems utilizing bus mastering for use with peripheral devices, the use of such a high bandwidth dedicated to the microprocessor may be considered unacceptable.
One solution for the bandwidth problem is to use a second architecture for caches referred to as the write-back architecture. In this architecture, when data is written to the cache, it need not necessarily be written to the main memory. The data may be retained only in the cache. The cache controller then monitors or snoops the bus activity during the operations of other bus mastering devices. In this case if a read request is sensed to an address where the only valid copy of the data is contained in the write-back cache, the cache controller then halts the cycle and provides the data to the main memory and to the device requesting the data. This is referred to as a write-back cycle based on a snoop hit. Write-back caches can remain off the bus and reduce bandwidth requirements until actual hits are noted, at which time a write-back operation occurs. Therefore more bus bandwidth may be available for other bus masters, thus potentially increasing the speed and efficiency of the computer system.
However, write-back cache controllers have other problems in that they are more complex because they must monitor the bus activity at all times and additionally the computer system must be designed such that the cycle which produces the write-back requirement must be somehow interruptable so that the data can be returned to the memory and to the requesting device. This puts limitations on the overall computer system design not necessarily present with the write-through caches. Thus for the potential performance increase there are certain design trade offs which must be made.
Other techniques are also being developed which help reduce the bus bandwidth required during microprocessor operations. One of these techniques is called a burst operation. During a burst, several sequential items of data are transmitted at a very high speed in rapid sequence. This is conventionally done by presenting only a single starting address and then bursting the remaining data portions, the burst sequence proceeding according to a predetermined pattern. This allows the memory controller to determine proper memory locations. A primary advantage of burst mode operations is that full addresses need not be provided after the initial cycle because burst operations are generally defined so that they occur only within a single page as defined for page mode DRAMs. Because of the operational characteristics of page mode DRAMs when operated only in page mode, that is requiring only column addresses, the memories are significantly faster then if a full address is supplied. Therefore this advantage is used by burst mode operations to help speed up access and transfer times. This burst mode of operation is utilized quite commonly with cache controllers because cache controllers are commonly defined as having a line width which is a certain number of bits. If the line width is defined such that it is multiple segments of the main memory width, i.e. 64 bit line for a 32 bit memory, then it becomes possible to perform burst cycles if a line in the cache needs to be filled or, in the case of a write-back cache, needs to be written. This burst mode operation has further complicated the design of the memory controller.
As an additional means of gaining performance in personal computers, the use of bus masters located in external card slots is being developed. Typically, high performance personal computers utilize one bus connected between the memory and the processing unit and a second bus which cooperates with the external, interchangeable circuit boards. One example of this external bus is the EISA or Extended Industry Standard Architecture, a superset of the ISA or Industry Standard Architecture first developed by International Business Machines Corp. in the IBM PC/AT. The EISA specification defines various timings and parameters of boards which cooperate with this architecture and over the bus. Numerous functions can be developed for cards which plug into an external bus, such as modem cards, network interface cards, hard disk drive control cards and so on. With the use of local processing on some of these cards, such as hard disk drive interface cards and video processing cards, very high effective data rates can be achieved. The local processor can perform significant processing functions in parallel with the central processor of the computer system. This parallel operation thus greatly improves the system performance. One common technique for these local processors to provide or obtain data is through what is called bus mastering. When a particular card is in a bus mastering mode it has taken control of the external bus, preferably the EISA bus, and has gained access to the various other buses required to access the main memory. In this case the bus mastering card is in complete control of the external bus cycles and thus is considered the master. In these instances, the central microprocessor of the computer system does not have any access to the main memory. However, when cache memory is utilized, the central microprocessor may continue operations until a cache miss is developed.
A problem can develop when these bus mastering cards are utilized in cooperation with a write-back cache controller. As is noted above, in conventional designs using a write-back cache controller, a special state or cycle is defined which is called an inhibit state which inhibits operation of the data requesting unit to allow the cache controller to provide data to the memories and possibly to the requesting device. Conventionally, when the inhibit indication is provided, the driving or controlling unit ceases driving the bus to allow the cache controller access. This inhibit state is not defined for the ISA or EISA buses. Therefore, potential problems arise when a write-back cache controller is utilized in cooperation with an EISA or ISA bus master. Some technique must be developed for providing data to the bus master should it request data that is contained only in the write-back cache. This requirement even further complicates the design of the memory controller so that it must understand not only bus masters, write-back caches and burst mode, but all of those in simultaneous operation. Therefore it is desirable that a memory controller be designed which can handle all of these simultaneous functions to allow maximum computer system performance.